Design and analysis of high-speed split-segmented switched-capacitor DACs

Design and Analysis of High Speed Capacitive Pipeline DACs

Design of a high speed capacitive digital-to-analog converter (SC DAC) is presented for 65 nm CMOS technology. SC pipeline architecture is used followed by an output driver. For GHz frequency operation with output voltage swing suitable for wireless applications (300 mVpp) the DAC performance is shown to be limited by the clock feed-through and settling effects in the SC array rather than by th...

High-Speed DACs

Low-Voltage High-Speed Switched-Capacitor Circuits Without Voltage Bootstrapper

Low-voltage high-speed switched-capacitor (SC) circuit design without using voltage bootstrapper is presented. The basic building block used for low-voltage SC circuit design is the auto-zeroed integrator (AZI), which can work at both low voltage and high sampling frequency. With this method, two low-voltage SC systems were successfully designed and implemented in 1.2m CMOS technology. The firs...

Switched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...

Comparator Design and Analysis for Comparator - Based Switched - Capacitor Circuits

The design of high gain, wide dynamic range op-amps for switched-capacitor circuits has become increasingly challenging with the migration of designs to scaled CMOS technologies. The reduced power supply voltages and the low intrinsic device gain in scaled technologies offset some of the benefits of the reduced device parasitics. An alternative comparator-based switched-capacitor circuit (CBSC)...